The present application relates to a circuit for providing improved electro-static discharge (ESD) protection for use in semiconductor devices and integrated circuits. ESD protection is presently provided to protect the internal circuitry of semiconductor devices in the presence of an electro-static stress event, such as a static discharge that occurs from a human body or machine approaching an electrically isolated device or circuit board. These ESD stress events may cause voltages in excess of the kilovolts range to be coupled to a pin of an integrated circuit. Without the ESD protection, the internal devices can be damaged or destroyed. The present application is directed to providing an improved ESD circuit and methods that effectively provide efficient and effective ESD protection.
In integrated circuits, ESD stress events must be protected against. ESD events occur when a charged object, such as a human body or another machine, is placed in proximity to an integrated circuit device and a static discharge occurs. The conductive leads on a packaged IC make an efficient surface for receiving electro-static discharge. If the voltage stress that is caused by the discharge into an integrated circuit pin is not protected against, physical damage including breakdown, metal electromigration, gate oxide rupture and other damage due to an ESD event stress may destroy or damage the physical devices within the integrated circuit.
Prior art ESD protection approaches involve a variety of circuit elements that are placed in proximity to the pads of the integrated circuit. Typically, a bond wire couples the input/output pad, which is a metallic or conductive surface, to a package pin. The pins may be gold, Alloy 42, copper, palladium and nickel plated material or the like. The ESD protection circuit provides a path to a safe terminal, typically a power supply pin or ground pin, and causes the electro-static current (called a “strike”) to bypass the susceptible semiconductor devices formed within the integrated circuit. An effective ESD circuit can protect a device and prolong its life.
The level of ESD protection needed for integrated circuits varies widely depending on the application and the type of integrated circuits. Circuits intended for use in automobile applications require particularly robust ESD protection. Similarly, integrated circuits that are intended to be handled by a consumer, such as flash cards and DIMM modules that a consumer physically inserts into a board or slot are particularly vulnerable to human body ESD strikes. In contrast, circuits that are installed into a robust circuit board inside a factory setting and placed on a well protected system in a highly controlled environment may require far less robust ESD protection. The work stations, workers, and the tools used in such an environment can be strapped to a ground terminal, and the humidity and materials used in the environment can be controlled to lower the probability of a static discharge event. In some cases, this protection may lower the ESD probability to a level such that on-board protection circuitry may not be required. This is a rare case, however, and most integrated circuits have some on-board ESD circuitry.
The electronics industry has created standards and classes for ESD ratings of devices, so that the purchasers of an integrated circuit may know what level of protection or class of ESD event the integrated circuit is designed for. These may be described as classes of protection for a human body model (HBM) event, for example. Class 0 may be for events from 0-2 kilovolts, Class 1 may be from 2 kilovolts to 4 kilovolts, Class 2 may be for greater than 4 kilovolts. Machine model (MM) events are also specified. This information is typically provided by an IC manufacturer so that the buyer understands what ESD stresses the device can withstand.
ESD events typically happen between an input, input/output or output pad and another terminal, either Vss (ground) and Vdd (positive power supply). Four modes of ESD stress are commonly described. A positive voltage from a pad to Vss may be referred to as a PS strike, a positive voltage from a pad to Vdd may be referred to as a PD strike, a negative voltage from a pad to Vss may be referred to as an NS strike, and a negative voltage from a pad to Vdd may be referred to as a ND strike. These descriptions will be used throughout this specification.
An effective ESD protection scheme must provide protective paths for each of these four modes of ESD stress. In addition, a path is often provided between the power supply pads; that is, from Vss to Vdd, and from Vdd to Vss. In the prior art, ESD protection circuits are provided at each protected pad. The pads are a conductive area formed on a surface of the integrated circuit for receiving an external connection, typically a bond wire or ball grid array (BGA) ball. The pads are then coupled by electrical conductors to internal circuitry. An input/output pad has an input path coupled to a driver circuit, usually a CMOS inverter, for receiving input voltage signals, and to an output path coupled to an internal buffer or inverter for driving an output; the circuit is arranged so that at a given time the PAD signal is either being received as an input signal or being driven at an output signal. An ESD protection circuit is placed at each of these many pads and thus prevents an ESD strike event from damaging the internal circuitry.
Prior art ESD protection circuits can take several forms but typically require, in addition to a path for the ESD current that bypasses the internal circuitry, a trigger circuit for each one protection circuit. Thus, prior art ESD protection circuits use a substantial amount of silicon area, and therefore reduce the available area for the application circuits in the integrated circuit. In addition, some prior art ESD circuits do not provide efficient paths for the ESD current to flow in all of the known modes, and therefore the ESD protection obtained is not as robust as is desired.
FIG. 1 illustrates a simplified system diagram of a known prior art circuit with ESD protection. In FIG. 1, a pad labeled PAD is coupled to an input/output buffer circuit 9. Circuit 9 includes an input buffer 5 for supplying incoming data to the remaining circuitry, an output signal OUT coupled to a CMOS inverter of PMOS transistor P1 and NMOS transistor N1, the input impedance Rin (which may be the parasitic or inherent impedance of the transistors that form buffer 5); and a signal coupled to PAD. An ESD protection circuit 11 is shown coupled to the PAD terminal. ESD protection circuit 11 is comprised of a first diode Dio_U, coupled between the PAD and the positive voltage supply VDD. A positive voltage ESD strike on the PAD will forward bias the diode Dio_U and a path will exist for ESD current to flow to the power supply terminal, bypassing the susceptible devices in the circuit 9, which is sometimes called the “victim” circuit. Diode Dio_D is coupled between the negative supply or ground VSS and the PAD. A negative voltage ESD strike at the PAD will forward bias Dio_D and current will flow from VSS to the PAD terminal, bypassing the circuitry in victim circuit 9. A circuit 17 is also shown. This circuit is referred to as a “power clamp” and provides ESD protection between the power supply terminals VSS and VDD. Inverter 13 will turn on a large FET transistor labeled “bigFET” during a positive event from VDD to VSS, providing a path for current to flow and protecting victim circuit 9. The values for R1 and Cl are chosen to cause the bigFET transistor to turn on for an appropriate event, but also chosen to try and keep it from turning on during normal switching operations. Diode Dio_CL provides a path from VSS to VDD for a negative voltage ESD strike between the power supplies. In a prior art integrated circuit, every pad will require ESD protection circuit 11, and there may be hundreds of signal pads to a large integrated circuit. However, the power clamp circuit 17 is not required at each pad and may be formed in one location on the integrated circuit, or alternatively several could be provided.
FIG. 2 illustrates the operations of the ESD protection circuits of FIG. 1 for the four modes of ESD strike described above. For a PS strike, positive from the PAD to VSS, the path for current is through two devices; Dio_U turns on and current flows to VDD, and then the bigFET transistor in the power clamp turns on and provides the path to VSS. This is not a direct path and so provides less than desirable results, a direct path through one device would be safer and faster; and is therefore more robust. For a PD strike, positive from the PAD to the supply VDD, the diode Dio_U is forward biased and provides a direct path. Similarly, for a negative strike at PAD with respect to VSS, the diode Dio_D is forward biased and provides a direct current path. Finally, for a negative strike ND from PAD to VDD, an indirect path through the bigFET transistor and then through diode Dio_D exists. Again, this indirect path is not preferred as the current must flow through two devices to reach the terminal, and this is less robust than a direct path and therefore provides less protection than desired.
Many ESD circuits rely on a silicon controlled rectifier (SCR) device to provide a current path. SCR devices are known in the art to be formed from p-n-p-n or n-p-n-p junctions. Once an SCR device is triggered, it will continue to conduct current so long as an adequate hold current is present, and the low on-resistance Ron for the SCR device and low triggering voltage makes them particularly useful in ESD protection circuits.
A known arrangement to provide the p-n-p-n structure for an SCR is to couple a pair of bipolar transistors, a p-n-p and an n-p-n, to provide the SCR. FIG. 3 illustrates a prior art ESD circuit using SCR devices. This circuit is described in a paper entitled “Substrate triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-um CMOS process”, IEEE Trans. Electron. Devices, vol. 50, no. 2, pp. 397-405, by Ker, et al.
In FIG. 3, input output terminal PAD is coupled again to an input/output buffer circuit 9. Circuit 9 has an inverter 5 providing the input signal to the remainder of an integrated circuit (the remaining circuitry is not shown), an inverter formed of P and N-MOS transistor P1 and N1 coupling the output data to the PAD, and an ESD protection circuit formed of an upper trigger 21, an upper SCR circuit 22, a lower trigger 24, and a lower SCR circuit 25.
SCR circuit 22 is coupled to an upper trigger circuit 21. Capacitor 34 and resistor 23 provide the trigger voltage to inverter 27, which when active, will pull down the base of p-n-p transistor 35, turning it on. Current flowing from the collector of p-n-p transistor 35 will create a positive voltage at the base of n-p-n transistor 31, turning it on and thus SCR circuit 22 will be triggered by the trigger circuit 21 in the event of a positive strike PD. Resistors 29 and 33, which act as bias resistors, are provided by the N-well (resistor 29) and P-well (resistor 33) that the bipolar transistors are formed in, and are not discrete resistor devices. Similarly, the lower trigger circuit 24 which is formed of resistor 41, capacitor 43, and inverter 47, will put a positive voltage on the base of n-p-n transistor 63 and cause current to flow from its emitter and through the resistor 53. Resistor 51 will also have current flowing through it which will, along with the voltage drop from the positive supply to the base of p-n-p transistor 61, cause transistor 61 to turn on and couple the PAD to the VSS through the SCR circuit 25. The lower trigger circuit will turn on when a positive voltage strike PS occurs, allowing the ESD current to flow into VSS.
In an integrated circuit using the ESD protection circuit of FIG. 3, each pad protected requires the two SCR circuits and the two trigger circuits. This requirement increases the silicon area utilized by the ESD circuits. Also, for the SCR circuits to rapidly turn on, the trigger circuits must use larger than normal transistors in the driving inverters, further increasing the silicon area required. Also, due to the configuration of these circuits, it is possible the ESD protection SCR circuits may trigger erroneously during normal switching at the pads of the device.
Prior art variations on these ESD circuits are known. In one variant, the trigger circuits use a so-called “Native NMOS” device to trigger the upper and lower SCR circuits. These native NMOS devices are also required for each pad, and they are turned off by an additional negative bias circuit; this must be done to prevent a large SCR current leakage. This approach does not reduce the silicon area required for the trigger circuitry.
In another prior approach, a chain of diodes is proposed as the trigger circuit. This approach is believed to require even more silicon area, as each pad requires a diode string for each SCR circuit. The diodes have to be large to provide fast SCR turn on during an ESD event. Because of the way the N type wells are biased in this circuit, a potential latch up problem exists. A reverse diode shunt is also required in parallel to the SCR circuits to provide NS (negative from the pad to VSS) and PD (positive from the pad to VDD) protection.
In another prior art approach, the trigger circuit is a NMOS device coupled to a dedicated gate bias circuit. Again, this approach requires a dedicated trigger circuit for each pad, resulting in a larger silicon area. In addition, the NMOS trigger transistor has to be sized larger than normal to provide rapid SCR circuit turn on during an ESD event. High standby current in the SCR circuit and a potential latch up problem again exists with this approach. Also, an extra diode shunt, placed in parallel to the SCR circuit, is needed for NS (negative from the pad to VSS) and PD (positive from the pad to VDD) protection.
A continuing need thus exists for an improved ESD protection circuit and methods that provide robust protection while reducing the amount of silicon area required for the protection circuitry.
The drawings, schematics and diagrams are illustrative, not intended to be limiting but are examples of embodiments, are simplified for explanatory purposes, and are not drawn to scale.